ELECTRONICS & COMMUNICATION DEPARTMENT

name of the department Electronics & Communication
course BE & ME
Year of starting 2001 (BE)
2010 (ME)
level UG & PG
1st year of approval by council 2000 749-87-104(E)/RC/95, 19/6/01 (BE)
2010 1-7937511/2010/EOA, 23/08/2010 (ME)
Year Wise Sanctioned Intake 120 (BE)
18 (ME)
name of the department Electronics & Communication
course BE & ME
Year of starting 2001 (BE)
2010 (ME)
level UG & PG
1st year of approval by council 2000 749-87-104(E)/RC/95, 19/6/01 (BE)
2010 1-7937511/2010/EOA, 23/08/2010 (ME)
Year Wise Sanctioned Intake 120 (BE)
18 (ME)
Name Dr. Rajesh A. Thakker
desgination Professor
Qualification B. E. (EC)
M. Tech. (Specialization: VLSI)
PhD (Specialization: VLSI)
Email address rathakker2008@gmail.com
Area of Interest Area of Interest : VLSI, Image Processing
publication Publication :
International Journals:
  • Subhash Patel, Rajesh A Thakker, Automatic Circuit Design and Optimization Using Modified PSO Algorithm, JOURNAL OF Engineering Science and Technology Review, 9 (1) (2016) 89-94, ISSN: 1791-2377 2016 Eastern Macedonia and Thrace Institute of Technology.
  • Shilesh Panchal, Rajesh Thakker, Implementation and Comparative Quantitative Assessment of Different Multispectral Image Pansharpening Approaches, Int. Journal on Signal and Image Processing, No. 5, Vol. 6, pp. 35-48, October 2015.
  • Sarman K. Hadia, R.A. Thakker and Kirit R. Bhatt, Implementation and comparative analysis of the optimisations produced by evolutionary algorithms for the parameter extraction of PSP MOSFET model, DOI:10.1080/00207217.2015.1067843, International Journal of Electronics, 07 Sep 2015, Taylor & Francis.
  • Chirag Sheth, Rajesh Thakker, "Performance Optimization of Network Firewalls by Rulebase Reordering based on Traffic Conditions," Vol. 2, No. 2, pp. 1 - 11, International journal of Computer Science & Network Solutions, Feb. - 2014, Journal ISSN : 2345-3397.
  • Chirag Sheth, Rajesh Thakker, "Performance Evaluation and Comparison of Network Firewalls Under DDoS Attack," International Journal of Computer Network and Information Security (IJCNIS), ISSN: 2074-9090 (Print), ISSN: 2074-9104 (Online), DOI: 10.5815/ijcnis.2013.12.08, 12, 60-67, 2013, MECS Publisher.
  • Rajesh A. Thakker, Mayank Srivastava, Ketankumar H. Tailor, Maryam Shojaei Baghini, Dinesh K. Sharma, V. Ramgopal Rao, Mahesh B. Patil, "A Novel Architecture for Improving Slew Rate in FinFET-based Op-Amps and OTAs," Microelectronics Journal, DOI: 10.1016/j.mejo.2011.01.010.
  • R. A. Thakker, C. Sathe, M. Shojaei Baghini, M. B. Patil, "A Table-based Approach to Study the Impact of Process Variations on FinFET Circuit Performance" IEEE Transactions on CAD, pp. 627-631, Vol. 29, April 2010.
  • R. A. Thakker, Maryam B. Shojaei, M. B. Patil, "Automatic Design of Low- power Low-Voltage Analog Circuits using Particle Swarm Optimization with Re-initialization", Journal of Low Power Electronics 5, American Scientific Publishers, 291-302 (October 2009).
  • V. Hariharan, R. Thakker, K. Singh, A. B. Sachid, M. B. Patil, J. Vasi and V. Ramgopal Rao, "Drain Current Model for Nanoscale Double-Gate MOSFETs", Solid State Electronics (Elsevier), Volume 53, Issue 9, pp. 1001-1008, September 2009.
  • R. A. Thakker, C. Sathe, A. B. Sachid, M. Shojaei Baghini, V. Ramgopal Rao, M. B. Patil, "A Novel Table-based approach for Design of FinFET Circuits ," IEEE Transactions on CAD, pp. 1061-1070, July 2009.
  • R. A. Thakker, M. B. Patil, and K. G. Anil, "Parameter Extraction for PSP MOSFET Model using Hierarchical Particle Swarm Optimization," Elsevier Journal on Engineering Applications of Artificial Intelligence, DOI: 10.1016/j.engappai.2008.07.001, pp. 317-328, Mar. 2009.

International Conferences:
  • Chirag Sheth, R. A. Thakker, Scalable Design of Open Source based Dynamic Routed Network for Interconnection of Firewalls at Multiple Geographic Locations, International Conference on ICT for Intelligent Systems (ICTIS 2015), Ahmedabad.
  • Mitesh Limachhia, Rajesh Thakker, and Nikhil Kothari, Analysis of FinFET based SRAM Cell Stability under Work Function Variability, 7th IEEE International Workshop on Reliability Aware System Design and Test 2016 (Jointly with 29th Int. Conf. on VLSI Design), Kolkata, Jan – 2016.
  • K.R.Trivedi, R. A. Thakker, 'Brainwave Enabled Multifunctional, Communication, Controlling and Speech Signal Generating System, International Conference on Electrical, Electronics, and Optimization Techniques (ICEEOT) – 2016, Chennai, Tamil Nadu, 3-5 March, 2016.
  • Jitendra B. Chinchore, Rajesh A. Thakker, “Design of Low Dropout Regulator Using Artificial Bee Colony Evolutionary Algorithm,” International Conference on Circuit, Power, Computing Technologies, Kumaracoil on the 19th - 20th of March 2015.
  • Chirag Sheth, R. A. Thakker, Scalable Design of Open Source based Dynamic Routed Network for Interconnection of Firewalls at Multiple Geographic Locations, International Conference on ICT for Intelligent Systems (ICTIS 2015), Ahmedabad.
  • Rachana A Patel, Rajesh A. Thakker, "Review of Contemporary Research in FinFET Technology," International Conference on Advances in Engineering 22nd - 23rd January 2015, Mehsana, Gujarat, India.
  • Amit C. Rathod, Rajesh A. Thakker, "FPGA Realization of Particle Swarm Optimization Algorithm with Floating Point Arithmetic," IEEE international conference on High performance computing and applications at Bhubaneswar, December 2014.
  • Kalpesh C. Chheladiya, Paresh N. Chavada [IEEE Student Member], Rajesh A. Thakker, "Switch-based Reconfigurable Photovoltaic Array for Power Maximization," Poster Category in International Conference on Emerging Electronics (ICEE), December - 2012.
  • Ravi C. Butani, Bhavin D. Gajjar, Rajesh A. Thakker, "Performance evaluation of Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) Algorithm," International Conference on Advanced Computing, Communication and Networks'11, pp. 108-112, June - 2011.
  • Chirag Sheth, R. A. Thakker, "Performance Evaluation and Comparative Analysis of Network Firewalls," accepted for publication Int. Conf. on Devices and Communication, Feb. 2011, BITs, Mesra, India, ISBN No. 978-1-4244-9189-6.
  • S. Prajapati, Niranjan Devashrayee, R. A. Thakker, M. Shojaei Baghini, M. B. Patil, "Performance Evaluation of FinFET and Planar MOSFET Devices at Circuit Level for 45nm Technology," IEEE/VSI VDAT Symposium 2010, India, July-2010.
  • R. A. Thakker, S. B. Prajapati, M. B. Patil, "Particle Swarm Optimization with Memory Loss Operation," accepted for publication in 2nd Int. Conf. on Computing, Communication and Networking Technologies (ICCCN), Tamilnadu, to be presented in July-2010.
  • A. B. Sachid, R. A. Thakker, M. Shojaei Baghini, D. K. Sharma, V. R. Rao, M. B. Patil, "Auto-BET-AMS: An Automated Device and Circuit Optimization Platform to Benchmark Emerging Technologies for Performance and Variability using an Analog and Mixed-Signal Design Framework," Proc. of 11th Int. Symposium on Quality Electronic Design (ISQED), San Jose, CA, USA, 22-24 March - 2010. ISBN: 978-1-4244-6454-8.
  • R. R. Navan, R. A. Thakker, S. P. Tiwari, M. Shojaei Baghini, M. B. Patil, S. G. Mhaisalkar, and V. Ramgopal Rao, "DC & transient circuit simulation Methodologies for organic electronics," in proceeding of 2nd Int. workshop on Electron Devices and Semiconductor, June 2009. ISBN: 978-1-4244-3831-0.
  • R. A. Thakker, C. Sathe, A. B. Sachid, M. Shojaei Baghini, V. Ramgopal Rao, M. B. Patil, "Automated Design and Optimization of Circuits in Emerging Technologies", IEEE ASP-DAC 2009 (Sister Conf. of DAC), pp. 504-509, Japan, Jan. 2009. ISBN: 978-1-4244-2748-2.
  • Rajesh A. Thakker, Chaitanya Sathe, Angada B. Sachid, Maryam Shojaei Baghini, V. Ramgopal Rao, Mahesh B. Patil, "A tool for automatic design of FinFET-based circuits," EDA Design Contest at the 22nd International Conference on VLSI Design, January 5-9, 2009.
  • R. A. Thakker, M. Shojaei Baghini, M. B. Patil, "Low-Power Low-Voltage Analog Circuit Design using HPSO", will be presented in IEEE Int. Conf. on VLSI Design 2009 (Sister Conf. of DAC), pp. 427-432, India, Jan. 2009. ISBN: 978-0-7695-3506-7.
  • A. B. Sachid, M. Srivastava, R. A. Thakker, M. Shojaei Baghini, D. K. Sharma, M.B.Patil, V. Ramgopal Rao, "Technology-Aware Design (TAD) for Sub-45nm CMOS Technologies", Intel Asia Academic Forum 2008, 20-22 Oct 2008, Taipei, Taiwan (received the best research paper award).
  • V. Hariharan, R. A. Thakker, J. Vasi, V. Ramgopal Rao, and M. B. Patil, "Closed Form Current and Conductance Model for Symmetric Double-Gate MOSFETs using Field Dependent Mobility," Workshop on Compact Modeling, NanoTech -2008, Boston, pp. 857-860, Vol. 3, June 2008. ISBN: 978-1-4200-8505-1.
  • R. A. Thakker, M. B. Patil, and K. G. Anil, "Parameter extraction for Advanced MOSFET model using particle swarm optimization," Workshop on Compact Modeling, NanoTech -2008, Boston, pp. 845-848, Vol. 3, June 2008. ISBN: 978-1-4200-8505-1.
  • A. M. Chopde, S. Khandelwal, R. A. Thakker, M. B. Patil, and Anil K. G., "Parameter extraction for MOS model 11 using particle swarm optimization," Proc. Int. Workshop Phy. of Semi. Dev., pp. 253-256, Dec. 2007. ISBN: 978-1-4244-1728-5.
  • R. A. Thakker, N. Gandhi, M. B. Patil, and K. G. Anil, "Parameter extraction for PSP MOSFET model using particle swarm optimization," Proc. Int. Workshop Phy. of Semi. Dev., pp. 130-133, Dec. 2007. ISBN: 978-1-4244-1728-5.
  • A. M. Chopde, S. Khandelwal, R. A. Thakker, S. S. Mande, and M. B. Patil, "Verification of Parameter Extraction Strategy for MOS model 11," Proc. Int. Conf. on Trends in Intelligent Electronic Systems, pp. 638-642, Nov. 2007.
  • R. A. Thakker and M. B. Patil, "Hierarchical particle swarm optimization with genetic operations and intensive local search," Proc. of Int. Conf. on Advances in Control and Optimization of Dynamical Systems, pp. 230-237, Feb. 2007.
  • D. Vinay Kumar, R. A. Thakker, M. B. Patil, and V. R. Rao, "Simulation study of non quasi-static behavior of MOS Transistors," 5th Int. Conf. Modeling and Simulation of Microsystems: Workshop on compact modeling, San Juan, Puerto Rico, pp. 742-745, April - 2002. ISBN No.: 0-9708275-7-1.

National Conference Papers
  • Rohit B. Vasoliya, Rajesh Thakker, SatyajitMohapatra, Nihar R. Mohapatra, Harishanker Gupta Digital Background Calibration using CFCS Technique for 3.5bits/stage 16-bit Pipelined ADC, NCERTE, 4th to 6th April – 2016, Chandkheda, Ahmedabad.
  • Rushabh Kothari, Darshana Mistry and Rajesh Thakker, Defect Detection in Smooth and Rough Surface of Plain Color Tile, NCERTE, 4th to 6th April – 2016, Chandkheda, Ahmedabad.
  • Hetal Bhatt, Rajesh A. Thakker, "Development of photovoltaic model for solar cell and array for different temperature environment and values of series resistance using MATLAB", SPCE National Conference, Feb - 2012.
  • Anand Patel, R. A. Thakker, "Medical Signal and Image Processing using Wavelet Transform," SPCE National Conference, Feb - 2012.
  • Hetal Bhatt, Rajesh A. Thakker, "MATLAB-based Simulation of Photovoltaic Solar Cell and its Array at Different Temperature Values," National Conference on Recent Trends in Engineering and Technology, May - 2011, Vallabh Vidyanagar.

Monograph/Book Published:
  • Rajesh A. Thakker, Mahesh B. Patil, Maryam Baghini Shojaei, "Applications Evolutionary Algorithms in VLSI," LAP LAMBERT Academic Publishing GmbH & Co. KG, ISBN 978-3-8454-0434-9, August/September - 2011

US Patent
  • Rajesh Thakker, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, "Operational Amplifier Having Improved Slew Rate" Patent No.: US 8,089,314 B2, Date of Issue: Jan. 3, 2012

European Patent:
  • Rajesh Thakker, Mayank Shrivastava, M. Shojaei, D. K. Sharma, V. Ramgopal Rao, M. B. Patil, "OPERATIONAL AMPLIFIER HAVING IMPROVED SLEW RATE," European Patent Application EP2543141, Publication Date: 01/09/2013

Patent filed:
  • Chirag Sheth, Rajesh Thakker, System and Method for Interconnection of Firewalls at multiple geographic locations through a Standalone Network, 384/MUM/2015, 5th February, 2015.
  • Priyank V. Virani, Nainesh P. Makwana, Suraj B. Sarvaiya, Prakash N. Solanki, Rajesh A. Thakker, and Chirag Sheth “ Low Cost, Wi-Fi Router and Mobile Handset based Intercom System,” April 2016.
  • Kiran Trivedi and Rajesh A. Thakker, Title of invention - - "Brainwave enabled multifunctional, communication, controlling and speech signal generating device," Indian patent submitted on 01/01/2013
Name Prof. Milind S. Shah
desgination Associate Professor
Qualification M.Tech (Electronics & Communication Engineering)
Email address mssvgec@gmail.com
Area of Interest Area of Interest : Communication Systems Engineering, Wireless Communication & Networks, Signal Processing
Name Prof. Alpesh H Dafda
desgination Assistant professor
Qualification M.E.
Email address sadafda@gmail.com
Area of Interest Area of Interest : Communication System
publication Publication :
International Journals:
  • Amit Patel and Alpesh H. Dafda, "Information hiding using HR-LR Algorithm", International Journal for Scientific Research and Development(IJSRD), Volume 2 Issue 3 May 2014, ISSN(Online): 2321-0613, pp. 1180-1184.
  • Amit Patel and Alpesh H. Dafda, "Information hiding technique using LSB substitution", International Journal for Scientific Research and Development(IJSRD), Volume 2 Issue 3 May 2014, ISSN(Online): 2321-0613, pp. 1176-1179.
  • Dr. Kiran Parmar and Alpesh Dafda, "Design of Satellite Communications Toolbox for MATLABË® in International Journal of Electronics and Computer Science Engineering (IJECSE), ISSN- 2277-1956, Volume 1 Number 2(April 2012), pp. 356-363.

National Conferences:
  • Janak Goswami and Alpesh Dafda, "Security aspects with AODV in WMANETs" in National Conference on Power Systems, Embedded Systems, Power Electronics, Communication, Control and Instrumentation(PEPCCI-2012) at Sardar Vallabhbhai Patel Institute of Technology - VASAD, ISBN 978-93-81286-06-7.
  • Alpesh Dafda and Janak Goswami, "Satellite Communications Security" in National Conference on Power Systems, Embedded Systems, Power Electronics, Communication, Control and Instrumentation(PEPCCI-2012) at Sardar Vallabhbhai Patel Institute of Technology - VASAD, ISBN 978-93-81286-06-7.
  • Dr. Kiran Parmar and Alpesh Dafda, "Interactive Learning in Satellite Communications using MATLAB" in National Conference on Advanced Electronic and Wireless Communication Technologies(NCAEWCT-2012), March 24-25, 2012 at Rajasthan College of Engineering for Women, Jaipur.

Monograph/Book Published:
  • Dr. Kiran Parmar and Alpesh Dafda, Basic Electronics, Mahajan Publishing House -Ahmedabad, January 2015, ISBN 978-93-83058-93-8.
  • Dr. G. H. Upadhyay and Prof. A. H. Dafda, Material Science and Metallurgy, Atul Prakashan - Ahmedabad, November 2009.
Name Prof. PATEL ALPESHKUMAR MANILAL
desgination Assistant Professor
Qualification M.Tech.
Email address am_patel@gtu.edu.in
Area of Interest Area of Interest : VLSI Design
Name Prof. JAYNILA P PRAJAPATI
desgination Assistant Professor
Qualification M.E.
Email address jayu_16582@yahoo.co.in
Area of Interest Area of Interest : Communication Systems
Name Prof. PATEL NARESHKUMAR PRAGJIBHAI
desgination Assistant Professor
Qualification M.Tech.
Email address np_patel@gtu.edu.in
Area of Interest Area of Interest : Analog and Digital VLSI Design
publication Publication :
  • Eaglekumar G. Tarpara, Jignesh Soni , Naresh Patel,"FPGA Based 1 Channel Fiber Optic Analog Signal link using 8B/10B Encoding Scheme"International conference on advances in electronics,computers and communications, Bangalore ,10-11 Oct 2014.
Name Prof. KETANKUMAR NAGINBHAI PATEL
desgination Assistant Professor
Qualification M.E.
Email address Kn_patel@gtu.edu.in
Area of Interest Area of Interest : Wireless Communication
Name Prof. Chintan B. dave
desgination Assistant Professor
Qualification M.E.
Email address cb_dave@gtu.edu.in
Area of Interest Area of Interest : VLSI
Name Prof. GAURAV ASARI
desgination Assistant Professor
Qualification M.E.
Email address grasari.vgec@gmail.com
Area of Interest Area of Interest : Antennas and Microwaves
Name Prof. Makwana Jagruti Jagdishbhai
desgination Assistant Professor
Qualification M.E.(E.C.)
Email address jagruti_ec@yahoo.com
Area of Interest Area of Interest : Communication Systems
Name PROF.SANGANI DHARA JASHVANTLAL
desgination Assistant Professor
Qualification M.E.(CSE)
Email address dsangani1987@gmail.com
Area of Interest Area of Interest : Image Processing,Speech processing,Signal processing
publication Publication :
  • Dhara J.Sangani,Arun Nandurbarkar, “ Pan sharpening of satelitte images with LBP and adaptive IHS basis” presented in First national conference on signal and Image processing , pune.(paper cited by International Journal for Computer Applications.(0975 – 8887)) and NCDISP-2015.
  • Dhara J.Sangani,Arun Nandurbarkar, “ Pan sharpening of satelitte images with LBP and adaptive IHS basis” selected in International conference on signal and image processing-Banglore.
  • Dhara J.Sangani,Arun Nandurbarkar, “Survry of Pansharpening of satellite images”Technix international journal for Engineering and reaserch.Vol.1,Issue-6.

Awards / Achievements:
  • Awards / Achievements Ex. Dean,Faculty of Engineering,HNGU, Patan,Vice-Chairman(2012-14)
  • Gold medalist in B.E.
Name Prof. CHAUHAN JYOTIKA DINESHBHAI
desgination ASSISTANT PROFESSOR (ADHOC)
Qualification B.E.
Email address JYOTIKADCHAUHAN@GMAIL.COM
Area of Interest Area of Interest : COMMUNICATION
Name Prof. Maitri j Patel
desgination ASSISTANT PROFESSOR(ADHOC)
Qualification B.E. (EC)
Email address maitripatel3010@yahoo.com
Area of Interest Area of Interest : Digital electronics,VLSI,microcontroller

Advance Communication Lab

This lab is used for performing experiments related to optical communication, mobile communication, Satellite communication, Microwave communication and Antenna subjects. The lab is fully equipped with the required kits to perform experiments.

Computer Center

This lab is used for performing experiments related to Digital signal processing, VLSI Technology and Design, computer networking subjects. The lab is fully equipped with various FPGA, CPLD trainer kits of various Xilinx families likes Spartan II, Spartan III, Vertex-4 and also with various Altera families� kits. The lab is also having DSP processor boards from TI to carry out minor and major projects in the area of Signal Processing.

Microcontroller and Microprocessor Laboratory

This lab is used for performing experiments related to Control Engineering, Embedded, Microprocessor and Microcontroller subjects. The lab is fully equipped with 8085, 8051, PIC and ARM processor kits with different interfacing modules such as LCD and keypad, stepper motor, A to D converter, GPIO interface, Programmable Peripheral Interface, DMA controller

Solid State Lab

This lab is used for performing experiments related to Basic electronics, circuits and networks, electronics workshops, integrated circuits and applications, digital electronics subjects. The lab is fully equipped with various kits and trainer board to perform experiments of related subjects.

Communication Laboratory

This lab is used for performing experiments related to electronics communication, digital communication, and power electronics subjects. The equipments like DSOs, CROs, Function Generators, and Communication Trainer Kits, SCR based kits are available in this laboratory.

ADDRESS

Vishwakarma Government Engineering College
Chandkheda,Ahmedabad
India - 382424
Ph : 079-23293866 , 23293006
FAX : 23293866
© 2015 Vishwakarma Government Engineering College , Chandkheda , Ahmedabad , India
Last Updated : 27/07/17